I. Field Of The Invention
The present invention relates to data transfer in a computer system, and more particularly, to optimizing time efficiency during a data transfer cycle in a data communication network.
II. Related Art
Many conventional communication networks and protocols are known in the art for the transfer of data in a computer system. Data in the context of this document refers to any type of information, including actual data, instructions, or the like, in whole or in part, and in a processed or unprocessed condition. Transfers of data can occur within a processor, memory board, or some other computer subsystem or between computer subsystems via, for example, electronic wiring, a bus network or a computer backplane.
FIG. 1 illustrates a general data communication network wherein n drivers 102,104 communicate to m receivers 106,108 via an interconnect network 110. The interconnect network 110 is biased by a terminal supply voltage V.sub.T. Moreover, the interconnect network 110 has an intrinsic characteristic impedance Z.sub.0, which is matched by a terminal resistance R.sub.T in order to minimize reflections on the interconnect network 110. The concept of minimizing reflections via a terminal resistance is well known in the art. Typically, the interconnect network 110 is terminated at both ends by a resistance R.sub.T equal to Z.sub.0. Thus, a driver sees a load impedance equal to R.sub.T /2 when it drives data onto the interconnect network 110.
Furthermore, in FIG. 1, it should be noted that one and only one of the n drivers 102,104 drives data on the interconnect network 110 at a given time. However, any number of the m receivers 106, 108 may participate in listening to the data being driven onto the interconnect network 110.
The n drivers 102, 104 are two-state devices. In order to transfer information from any of the n drivers 102,104 to one or more of the m receivers 106, 108 the active driver either pulls the interconnect network 110 to ground potential to indicate a logic low ("0") or exhibits a high resistance (resistance=&gt;infinity) to indicate a logic high ("1").
More specifically, consider the scenario when the driver 102 is active. When the active driver 102 wishes to indicate a logic low, it pulls the interconnect network 110 to ground potential by sinking the current I.sub.O into the driver 102. Because of the current flow I.sub.O, the voltage (approx. V.sub.T) appearing on the interconnect network 110 is substantially diminished. Conceptually, the logic signal is sent in one direction while the current I.sub.0 travels in the opposite direction. Worth noting is that a time delay exists between the point at which the driver 102 initiates transfer of the logic signal and the point at which the interconnect network 110 ultimately exhibits the intended logic low. The time delay depends largely upon both the internal impedance of the driver 102 and the characteristic impedance of the interconnect network 110. In the convention, the trend has been to steadily decrease the internal impedance of the drivers 102, 104, which are usually integrated circuits (IC), so as to increase the network speed.
In contrast, when the active driver 102 wishes to indicate a logic high by exhibiting a high resistance, the current I.sub.T equals approximately zero, and accordingly, the voltage V.sub.T appears on the interconnect network 110. Further, a time delay exists between the point at which the driver 102 initiates the logic high and the point at which the interconnect network 110 will exhibit the intended logic high.
FIG. 2 illustrates an example of a timing diagram for the data communication network of FIG. 1. As illustrated in FIG. 2, the 1st driver 102 may take control of the interconnect network 110 for a number of interconnect network cycles, and then, relinquish control of the interconnect network 110 to the nth driver 104, which can then control the interconnect network 110 for any number of cycles. When a driver takes control of the interconnect network 110, i.e., reads or writes data, in the convention the driver is said to have "mastership", "tenureship", or "ownership" of the interconnect network. Furthermore, during mastership of the interconnect network 110, time must be allocated to the necessary features of driver delay, interconnect network delay, receiver setup time for latching data, and a few other minor considerations. In the art, the trend is to make each cycle as fast as possible so as to increase the speed of the overall system, while providing for the preceding features.
As further shown in the example of FIG. 2, the 1st driver 102 controls the interconnect network 110 for interconnect network cycles 1 and 2, and then relinquishes control in cycle 3. In other words, a "change over" in mastership has occurred. Significantly, a "dead time", or wait period, as indicated by reference numeral 202, must be inserted in cycle 3, just before the nth driver 104 takes control of the interconnect network 110. The wait period must be inserted in order to avoid driver conflicts and provide proper transmission of logic signals. The wait period is undesirable because it slows the data communication network.
One solution to eliminate the wait period 202 required in cycle 3 is to uniformly increase the time periods of the cycles to allocate some time for a change-over in mastership. For instance, in the example of FIG. 2, the 1st driver 102 would terminate its mastership during cycle 2, and not in cycle 3, so that the nth driver 104 could take control of the interconnect network 110 at the beginning of cycle 3. The foregoing solution would be adequate in systems where driver change-overs occur very often. However, this solution is inadequate in many communication networks where drivers take control of the interconnect network 110 for a number of cycles. In such communication networks, the active driver having control of the interconnect network 110 pays a performance penalty (change over time) during each cycle it has control. The performance penalties for each cycle aggregate into an undesirable amount of wasted time.